The switching speed of a computer bus often determines the overall system performance. For example, the computer may include multiple central processing units (CPU) module, multiple input/output (I/O) modules, and multiple memory modules. Each module communicates with the other modules via a bus, which is a set of parallel electrical signal paths. In a typical operation performed by the computer, a data word is read from the memory and then passed along the bus to the CPU for an arithmetic operation, and the CPU module then forwards the results of the operation back along the bus to the I/O module for output. The signal propagation characteristics of the bus, including both delay and settling time, thus determine the overall system speed, since the faster that data signals are transmitted and settled on the bus, the faster the system completes a particular task.
Perhaps the most common digital integrated circuit (IC) technology in use today is so-called complimentary metal oxide semiconductor (CMOS). Historically, the designers of some electronic systems interconnect the CMOS circuits on several different modules without special consideration of the impedance presented by the bus signal paths. While this is not of particular concern where the logic switching speeds are several orders of magnitude less than the bus propagation delay, it does become a problem for high performance systems, which may require switching speeds of 50 MegaHertz (MHz) or more over a bus which is a foot or more in length.
A failure to either properly terminate bus connections or to properly match impedances typically manifests itself as an increase in settling time. This is because the resultant overshoot and ringing must be allowed to settle before a bus receiver circuit may properly detect the data bit transmitted by a bus driver circuit. As a result, an extra delay must be added to the system bus cycle time to insure that the data bit may be detected at the receiver.
The settling time can be reduced somewhat if each bus signal path is treated as a transmission line having certain delay and energy storage characteristics. For example, it is well known that a transmission line terminated in its characteristic impedance reduces the settling time. Settling time can also be minimized by using a "party-line" type bus, that is, a bus where the drivers have open drain (for MOS circuit technologies) or open collector (for bipolar circuit technologies) output transistors which are connected through a common termination resistor to a termination supply voltage. With such a bus, one of the logic levels is represented by a non-asserted state, where the open drain/collector transistors are turned off.
However, there remains some question as to the optimum way to properly terminate a high performance bus. In particular, terminating the bus at each end may require placing the termination impedances on a centerplane or backplane, where it may or may not be convenient to mount discrete components. Alternatively, the termination impedances may be placed in the two circuit board modules on the extremities of the bus, but this has the disadvantage of requiring special variants of the modules when they are used at the ends of the bus. Another difficulty occurs when the system design dictates that each module have its own termination supply voltage, which means that the end termination technique can be difficult to implement.
A distributed termination technique has been used, in some applications, where each bus path in each module is terminated in the characteristic impedance of the bus. The distributed termination technique works reasonably well, but is not without its own problems. In particular, each driver must supply enough current to drive all of the termination impedances connected to the bus. This is not of particular concern in a small system having only a few modules, but as the number of modules increases, the extra current drive requirements increase the bus settling time.
There are several other considerations which further complicate the design of a bus. Often times, it is necessary to provide a "tri-statable"driver which has a separate disable input that causes the driver to release, or deassert, the bus. To provide this function, an extra transistor stage must be added to the output circuit in the bus driver, which adds propagation delay.
Furthermore, it is often desirable to provide a control signal that permits the driver to be disabled, for system test purposes. This permits the system to be tested by selectively disabling the drivers, to determine if any particular driver is "stuck", or failing to release the bus when it should. This usually means that another stage of transistors must be placed in the critical delay path of the driver.
All of these considerations are exacerbated when the bus drivers and receivers must be designed using the transistors available on standard Application Specific Integrated Circuits (ASICs) or gate arrays. The circuit designer is restricted in the number of transistors and the sizes available in such a situation.
What is needed is a distributed termination, bus driver/receiver circuit that minimizes bus propagation time. The circuit should provide an open drain output which may be disabled, as well as placed into a test state, without adding logic delays in the critical path of the driver. The design should be easily adaptable to standard gate arrays and ASICs by using only standard transistors.